Most current CPU architectures, including the PowerPC™ architecture, limit the number of architecturally visible registers (both general purpose registers, or GPRs, and floating point registers, or FPRs) to a small number N (with N≦32 in general for RISC architectures). While these architectural registers may be backed up by a larger pool of physical renaming registers, the compiler (or assembly language programmer) must make register allocation and spilling decisions using only (N-K) general-purpose registers, where K is the number of registers reserved for specific uses by the application binary interface. This limitation on the number of architected registers increases register pressure, increases the number of register spills and restores, and limits the use of program transformations requiring a large number of registers (such as unroll-and-jam).
Fixed length instructions and dense instruction encoding are key features of RISC architectures. For example, the PowerPC™ ISA (instruction set architecture) uses 32 bits to encode an instruction, with five bits allocated for each register specifier. In this architecture, instructions have between one and four register sources and destinations, such that there are only 12 bits remaining to encode the operation. Instruction encoding is tight, so that any attempt to increase the width of the register specifier fields would result either in longer instructions and code bloat, or in two-address instructions rather than the traditional RISC three-address instructions. We now discuss some known solutions to the problem of encoding register specifiers to increase the number of usable registers.